The disclosure relates generally to semiconductor device package assembly, and more particularly to a ring structure for flip chip packaging.
In the microelectronics industry, a chip carrying an integrated circuit is commonly mounted on a package carrier, such as a substrate, a circuit board or a leadframe that provides electrical connections from the chip to the exterior of the package. In one such packaging arrangement called flip chip mounting, the chip includes an area array of electrically conductive contacts, known as bond pads that are electrically connected to corresponding area array of electrically-conductive contacts on the substrate known as solder bumps. Typically, the solder bumps are registered with the bond pads and a reflow process is applied to create electrical connections in the form of solder joints between the chip and the substrate. The process of flip chip mounting results in a space or gap between the chip and the substrate.
The chip and the substrate are usually formed of different materials having mismatched coefficients of thermal expansion (CTE). As a result, the chip and the substrate experience significantly different dimensional changes when heated that creates significant thermally induced stresses in the electrical connections between the chip and the substrate. If uncompensated, the disparity in thermal expansion can result in degradation in the performance of the chip, damage to the solder joints, or package failure. As the size of the chip increases, the effect of a mismatch in the coefficient of thermal expansion between the chip and the substrate becomes more pronounced. In stacked die packages, the mismatch in coefficient of thermal expansion between the die laminate and the package may be even greater than in single die packages. The failure mechanism in stacked die packages may shift from solder joint damage to die damage.
To improve the reliability of electrical connections in flip chip package assemblies, it is common in the microelectronics industry to fill the gap between the chip and the substrate with an encapsulant material, or underfill. The underfill increases the fatigue life of the package and improves the reliability of the electrical connections by reducing the stress experienced by the electrical connections during thermal cycling (e.g., changes in temperature) or when the chip and the substrate have a significant temperature differential.
To further enhance the rigidity of the package assembly, stiffeners are often employed in the package assembly. A stiffener (also sometimes referred to as a “picture frame”) is a rigid ring-like structure made from a material such as metal having substantially the same dimensions as the package substrate with a window in its center to clear the chip. The stiffener attaches on the substrate and surrounds the chip to constrain the substrate in order to prevent its warpage or other movement relative to the chip, which may be caused by thermal cycling during package assembly, reliability testing, or field operation. Even with the use of the stiffener in the flip chip package, however the package may still suffer warpage to some degree. Moreover, as it is the natural tendency of the substrate to warp during thermal cycling, testing or operation, sometimes into a convex shape, with the attachment of the stiffener to the substrate stress may be imposed on the substrate as it is being constrained by the stiffener. The warpage and stress in the chip or package may lead to chip performance degradation or package failure.
For these reasons and other reasons that will become apparent upon reading the following detailed description, there is a need for an improved flip chip package that overcomes the problems discussed above.